Designing small, fast, low-power, and reliable logic circuits is becoming more difficult with scaling. Integrated logic circuits on silicon on insulator (SOI) substrates are beginning to find increasing usage in an effort to achieve these goals. SOI refers to a silicon substrate where the top layer (in which the devices are fabricated) is separated from the “bulk” portion of the substrate by a insulator layer. This can be contrasted with bulk silicon substrates which have no buried insulator layer. In bulk CMOS circuits, NMOS transistors are fabricated in p-type wells and PMOS devices are formed in n-type wells with both well structures formed in the substrate. These well structures provide the electrical isolation required between the NMOS and PMOS transistors in CMOS logic circuits. The spacing requirement of these well structures for proper electrical isolation in bulk CMOS logic circuit fabrication has led to grouping of NMOS and PMOS transistors to maximize circuit density. In bulk CMOS circuits, basic transistor networks performing logic functions can be classified as the following three types: pull-up network (PUN), which conditionally forms a current path between the output node and the circuit power supply, pull-down network (PDN), which conditionally forms a current path between the output node and the circuit ground, and pass-transistor network (PTN), which conditionally forms a current path between the output node and the pass inputs. In general only PMOS transistors are used in a PUN, as shown in FIG. 1(a), only NMOS transistors are used in a PDN, as shown in FIG. 1(b), and only PMOS or only NMOS transistors are used in a PTN, as shown in FIG. 1(c). In FIG. 1(a) the PUN 15 comprises a circuit of PMOS transistors. The input terminals 25 represent the logic input terminals. Given certain input logic signals, the PUN will force the output 10 to approach the supply voltage VDD 5. In FIG. 1(b), the PDN 20 comprises a circuit of NMOS transistors. For certain input logic signals applied to the PDN input terminals 26, the PDN will force the voltage on the output terminal 12 to approach the voltage VSS 30. In most cases the voltage VSS is the circuit ground voltage of zero volts. In FIG. 1(c) the first PTN 50 comprises PMOS transistors and the second PTN 55 comprises NMOS transistors. For certain control signals applied to the control inputs 45, either the first PTN 50, the second PTN 55, or both will pass the signal on the input terminals 40 through to the output terminal 35. In early NMOS logic circuits, both enhancement and depletion mode NMOS transistors were used as pull up devices. In these NMOS circuits however, the gate of the enhancement transistor was connected to a fixed voltage (usually the supply voltage) and the gate of the depletion transistor was connected to the output node.
Conventional SOI logic circuits are based on bulk CMOS logic with conventional SOI circuits and bulk CMOS circuits sharing the same circuit topology. Thus in conventional SOI logic circuits, only PMOS transistors are used in a PUN, only NMOS transistors are used in a PDN, and only PMOS or only NMOS transistors are used in a PTN. This circuit layout and design methodology while optimized for bulk CMOS circuits does not take full advantage of the unique properties of SOI substrates. A new circuit design methodology is therefore required that fully utilizes the properties of SOI substrates for CMOS logic circuits.